Unknown instructions execute with no illegal instruction exception raised

Created by: salaheddinhetalani

Issue Description

Illegal instruction exception is not raised for unknown instructions that have the opcode of an F instruction.

Component

Component:RTL

RISC-V Specification

The Zfinx extension adds all of the instructions that the F extension adds, except for the transfer instructions FLW, FSW, FMV.W.X, FMV.X.W, C.FLW[SP], and C.FSW[SP].

The Zfinx variants of these F-extension instructions have the same semantics, except that whenever such an instruction would have accessed an f register, it instead accesses the x register with the same number.

Steps to Reproduce

As shown below, the following sequence of instructions happens:

32'h4813f053

The unknown instruction 32'h4813f053 that has the opcode of F instructions 8'h53 is decoded at t##0 and executed updating the integer register file at t##1 with no illegal instruction exception being raised, as the associated CSRs highlighted are not updated. This is true when the the 5 MSB of the decoded instruction are 5'b01001, 5'b01000 or 5'b01010.

Top Level Parameters

cv32e40p_wrapper #(
    .PULP_XPULP       (0),
    .PULP_CLUSTER     (0),
    .FPU              (1),
    .PULP_ZFINX       (1),
    .NUM_MHPMCOUNTERS (1)
)

Git Hash: https://github.com/openhwgroup/cv32e40p/commit/d0d1c25374e3770c4335568ef16e84404cedbdea Flist: cv32e40p_fpu_manifest.flist VCD: bug_4.vcd

Product: OneSpin 360 DV-Verify App: Processor Verification App Tool's version: 2022.3_1