Wrong data memory access of misaligned memory instructions caused by multicycle F instructions

Created by: salaheddinhetalani

Issue Description

Misaligned memory instructions causing multiple memory accesses set wrong second memory access in case they are preceded by a multicycle F instruction.

Component

Component:RTL

RISC-V Specification

The Zfinx extension adds all of the instructions that the F extension adds, except for the transfer instructions FLW, FSW, FMV.W.X, FMV.X.W, C.FLW[SP], and C.FSW[SP].

The Zfinx variants of these F-extension instructions have the same semantics, except that whenever such an instruction would have accessed an f register, it instead accesses the x register with the same number.

Steps to Reproduce

As shown below, the following sequence of instructions happens:

fsqrt.s x21, x17, RDN -> lw x24, -2(x18)

The load instruction sets the memory access at t##1 correctly, setting the address to 32'ha0001ffd. However, at t##3 the second access address is set wrongly to 32'h80000004 instead of the correct value of 32'ha0002000. It seems the value written into x21 by the previous fsqrt.s instruction is taken into consideration, 32'h80000000, while setting the address of the second memory access.

Top Level Parameters

cv32e40p_wrapper #(
    .PULP_XPULP       (0),
    .PULP_CLUSTER     (0),
    .FPU              (1),
    .PULP_ZFINX       (1),
    .NUM_MHPMCOUNTERS (1)
)

Git Hash: https://github.com/openhwgroup/cv32e40p/commit/d0d1c25374e3770c4335568ef16e84404cedbdea Flist: cv32e40p_fpu_manifest.flist VCD: bug_2.vcd

Product: OneSpin 360 DV-Verify App: Processor Verification App Tool's version: 2022.3_1