Wrong instruction fetch caused by multicycle F instructions | Forwarding issue

Created by: salaheddinhetalani

Issue Description

Jump instructions set the wrong PC in case they are preceded by a multicycle F instruction and their source register is the same destination register of the floating point one.

Component

Component:RTL

RISC-V Specification

The Zfinx extension adds all of the instructions that the F extension adds, except for the transfer instructions FLW, FSW, FMV.W.X, FMV.X.W, C.FLW[SP], and C.FSW[SP].

The Zfinx variants of these F-extension instructions have the same semantics, except that whenever such an instruction would have accessed an f register, it instead accesses the x register with the same number.

Steps to Reproduce

As shown below, the following sequence of instructions happens:

fdiv.s x8, x0, x0, RDN -> fle.s x10, x7, x19 -> jalr x13, x8, -115

The first instruction updates x8 register (Zfinx is set) with the value 32'h7fc00000 (NaN result of division by 0). When jalr instruction is executed, it sets the PC wrongly to 32'hffffffc2, which is the value of adding the immediate 32'hffffff8d to the old content 32'h36 of x8. The correct PC should be 32'h7fbfff8c, resulting from adding the immediate 32'hffffff8d to the new content 32'h7fc00000 of x8.

Top Level Parameters

cv32e40p_wrapper #(
    .PULP_XPULP       (0),
    .PULP_CLUSTER     (0),
    .FPU              (1),
    .PULP_ZFINX       (1),
    .NUM_MHPMCOUNTERS (1)
)

Git Hash: https://github.com/openhwgroup/cv32e40p/commit/d0d1c25374e3770c4335568ef16e84404cedbdea Flist: cv32e40p_fpu_manifest.flist VCD: bug_1.vcd

Product: OneSpin 360 DV-Verify App: Processor Verification App Tool's version: 2022.3_1