Please update the User Manual to clarify "interrupt occurs during step" behavior

As discussed in core-v-verif issue 904, the specified behaviour in Debug Spec 0.13.2 for a RISC-V core when an interrupt occurs while the core is stepping is somewhat ambiguous. After the 0.13.2 spec was released, this ambiguity was discussed in:

https://github.com/riscv/riscv-debug-spec/issues/510 https://github.com/riscv/riscv-debug-spec/issues/511

Debug Spec 1.0.0 clarifies the expected behaviour of a core (Section 4.1.1). The CV32E40P is not compliant with this section of the 1.0.0 spec, and it was agreed that the CV32E40P User Manual should be updated to reflect this. I leave it to others to determine whether this should be classified as an errata against 1.0.0, or a clarification against 0.13.2.

Historical context is provided in the attachment: cv32e40_debug_issue(14-oct-2021).pdf