CV32E40P Decoder Tolerating Xpulp_NN ISA
Created by: OmarAlsherbini
Hello everyone,
The current decoding implementation of the CV32E40P decoder is very tolerant for OPCODE_VECOP (7'h57), allowing it to tolerate any instruction as long as its func6 (instr[31:26]) is recognized. This, in turn, recognizes Xpulp_NN ISA to be legal instructions - without correct ALU/MUL/FPU support from the core - which denies the opportunity to integrate dedicated Xpulp_NN accelerators via X-Interface to decode these instructions agnostically and execute them there.
The following version of the decoder is a proposed solution to this problem developed on my fork of the repository: https://github.com/OmarAlsherbini/cv32e40p/blob/master/rtl/cv32e40p_decoder.sv
This implementation has been tested with Xpulp_NN ISA to indeed solve this problem. It also has been tested for one Xpulp instruction to be still recognized and functioning properly (cv.sll.sc.h). The testing program and the makefile additions to be appended to the TB's makefile can be found here: