interrupt handler entry after CSRRC instruction clears local interrupt

Created by: strichmo

It is not completely clear to me whether this is an architectural bug, or simply a scenario where I need to tune the ISS to.

In this case, the CSRs are being written to (including MIE and MSTATUS.MIE) while external interrupts are being generated randomly. In this particular case an external interrupt [29] is being asserted one cycle before mie[29] is being disabled via a CSRRC write. The interrupt controller sees the single cycle of enabled interrupt [29] and initiates its state machine to enter the interrupt. The CSRRC completes and then the interrupt is jumped to (0x4a774). The test fails because the ISS is seeing the updated MIE value and does not think [29] is enabled. However that is separate testbench issue.

My question is architecturally does clearing an MIE signal a critical section for IRQ[29] (or perhaps in general for all interrupts for MSTATUS.MIE or any combinations of interrupts)?

If the pipeline were to execute one more instruction before taking the interrupt then there is no question there is an architectural violation, but so far I have not observed such a case.

Component:RTL

Steps to Reproduce

To reproduce, clone my fork at: https://github.com/strichmo/core-v-verif/tree/strichmo/pr/rand_interrupt_wfi Hash: 6446d0f0a02b1a491b75854cc5963743fa6caf67

% makecv32 comp_corev-dv gen_corev-dv test TEST=corev_rand_interrupt WAVES=1 SEED=204713540 COMP=1 CFG=no_pulp USER_RUN_FLAGS=+UVM_MAX_QUIT_COUNT=30,NO