Address is changed in ongoing request on instruction bus

Created by: felixmiller

This is related to this pull request: https://github.com/pulp-platform/zero-riscy/pull/7 However the issues shows for both the zeroriscy and the ri5cy core.

When a branch instruction is encountered (and the branch is taken) the prefetch unit immediately puts the new address on the instruction bus when the prefetch unit is currently in the WAIT_GNT state.

Relevant sources: ri5scy: https://github.com/pulp-platform/riscv/blob/master/rtl/riscv_prefetch_buffer.sv#L264 zeroriscy: https://github.com/pulp-platform/zero-riscy/blob/master/zeroriscy_prefetch_buffer.sv#L149

We see this issue causing problems in our implementation only when both the branch_i and the instr_gnt_i signal are asserted in the same cycle. However, also if the address is changed earlier (when the instr_req_o signal already has been asserted but before instr_gnt_i is received) the question remains if the protocol specification (from the user's manuals for the zeroriscy and the ri5cy core) allows this behavior.

The timing below shows this behavior when using the zeroriscy core. The address can change as late as the instr_gnt_i signal is received or at an earlier time in the WAIT_GNT state of the prefetch unit (2nd diagram).