cv32e40p_register_file_test_wrap has unused BIST ports
Module cv32e40p_register_file_test_wrap
has a set of un-used BIST ports. It is instantiated in module cv32e40p_id_stage
:
cv32e40p_register_file_test_wrap
#(
.ADDR_WIDTH(6),
.FPU(FPU),
.PULP_ZFINX(PULP_ZFINX)
)
registers_i
(
.clk ( clk ),
.rst_n ( rst_n ),
// sniped port-map....
// BIST ENABLE
.BIST ( 1'b0 ), // PLEASE CONNECT ME;
// BIST ports
.CSN_T ( 1'b0 ), // PLEASE CONNECT ME; Synthesis will remove me if unconnected
.WEN_T ( 1'b0 ), // PLEASE CONNECT ME; Synthesis will remove me if unconnected
.A_T ( 6'b0 ), // PLEASE CONNECT ME; Synthesis will remove me if unconnected
.D_T (32'b0 ), // PLEASE CONNECT ME; Synthesis will remove me if unconnected
.Q_T ( )
);
As far as I am aware, this is the only BIST interface in the core and the test_wrap is the only module that provides (or needs) BIST access. Also, BIST is not mentioned in the User Manual. I recommend that we either:
- Remove the BIST logic and ports altogether, or,
- Bring these ports to the top-level of the core and document their use in the User Manual.
This issue was found by looking at holes in code coverage from a Compliance test-suite regression run on the 6fbd88c6 hash of this repo.