Illegal Instruction Exception not Raised - URET

Created by: shetalani

RISC-V Specification:

3.2.2: "URET is only provided if user-mode traps are supported, and should raise an illegal instruction otherwise."

Issue Description:

Executing URET instruction when U mode isn't supported doesn't raise an illegal instruction exception.

Example:

As shown below, the instruction 32'h00200073 (URET) is decoded at time point t##0, where MSTATUS, MCAUSE and MEPC are not updated to reflect the illegal exception.

Top Level Parameters

cv32e40p_core #(
    .FPU                      ( 0 ),
    .NUM_MHPMCOUNTERS         ( 1 ),
    .PULP_CLUSTER             ( 0 ),
    .PULP_XPULP               ( 0 ),
    .PULP_ZFINX               ( 0 )
)

Product: OneSpin 360 DV-Verify App: RVV Tool's version: 2020.1.4