HPM counter logic 'possibly' not implemented correctly

Created by: silabs-PaulZ

@davideschiavone ,

This issue was found by inspecting the RTL. It also serves as a reminder to write a test for HPM. The RTL looks to increment the jump, branch, and branch_taken based on a signal asserted during the decode phase (e.g. jump_i) along with a pipelined control signal (id_valid_q).

https://github.com/openhwgroup/cv32e40p/blob/1607d8b675864db1aa013364fd4444a665331830/rtl/cv32e40p_cs_registers.sv#L1352-L1363

Perhaps this should be replaced with the non-pipelined instruction retired condition (e.g. jump_i & id_valid_i & is_decoding_i). hash: 8a626b91