Simultaneous request of debug, trigger, and interrupt
Created by: silabs-PaulZ
The controller state machine has a bug where it cannot handle an interrupt and either debug or trigger being requested at the same time. The FSM is encoded in a one-hot manner, expecting only one of these conditions to be active. Moreover, an assertion was previously written to catch this overlap but has been inadvertently disabled.
The proposal to fix this is to replace the unique case with if then else; higher prioirity on debug,trigger, interrupt, then other.
Also, we should remove the invalid assertion. assert property ( @(posedge clk) (~('0 & irq_req_ctrl_i)) ) else $warning("Both dbg_req_i and irq_req_ctrl_i are active");
git hash: 916d92af
