Debug spec - Trigger registers access

Created by: mp-17

Hello everyone,

I saw that the decoder of cv32e40p allows access to the trigger registers only when the core is in debug mode. RISC-V Debug Specification states that they can be accessed in machine mode as well:

The trigger registers are only accessible in machine and Debug Mode to prevent untrusted user code from causing entry into Debug Mode without the OS's permission.

(RISC-V External Debug Support, Version 0.13.2d5029366d59e8563c08b6b9435f82573b603e48e, page. 48, par. 5.2)

I've not checked yet if there are also other registers with access restriction problems.

Thank you and best regards, Matteo