p.elw rD, Imm(rs1!) should not exist

Created by: Silabs-ArjanB

Currently two flavor of p.elw are in the RTL:

p.elw rD, Imm(rs1!)
p.elw rD, Imm(rs1)

The encoding that currently is interpreted as p.elw rD, Imm(rs1!) should trigger an illegal instruction instead. See also https://github.com/openhwgroup/core-v-docs/issues/99