Debug_req pulse width (bug)

Created by: silabs-PaulZ

If the debug_req input signal is asserted for less than 5 clocks, the core does not properly enter debug mode. Depending on the pulse width, the core may fetch from the debug address (DM_HALT_ADDRESS) but may not the internal debug_mode bit.

The solution is to do one of the following:

1. Document a requirement that the debug_req must be asserted more than 5 clocks (which is reasonable assumption that debug_req is typically asserted for much longer, but may not cover all SOC implementations in the future and can lead to deadlock scenarios if not strictly adhered to)
2. Add a sticky debug_req capture register that is asserted until debug_mode is entered. It should then be cleared when debug_mode==1 and debug_req=0. This is a more robust solution to handle corner cases (especially shown in random verification)