Rename clock gating module

Created by: davideschiavone

The file is called sim, which is correct as it is meant to be a simulation-only file. Not for synthesis.

The module though, should not have the sim name as it should be replace by a technology file where the real clock gating cell should be instantiated instead.

In that case, the tech file should be a SV file called cv32e40p_techname_clock_gating.sv which instantiate the CG cell. The module name of the wrapper should be the same as the simulation one.