if rs1=x0 both CSRRS and CSRRC will not write to the CSR at all

Created by: colin4124

In RISCV privileged specification v1.7 2.1 Instructions to access CSRs:

For both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write. Note that if rs1 specifies a register holding a zero value other than x0, the instruction will still write the unmodified value back to the CSR.

I found csr_we_int in cs_registers.sv, it just depend on csr_op_i.