Different behavior of spike and design on c.jr zero instruction

Created by: dspg-arch1

On processing this instruction, design performs jump operation to address 0x0. We can see it on the waveform. But implementation of this instruction in the spike has additional require statement which marks it as illegal instruction. The link to c.jr instruction implementation in the github is: https://github.com/riscv/riscv-isa-sim/blob/master/riscv/insns/c_jr.h (shown here) 1 require_extension('C'); 2 require(insn.rvc_rs1() != 0); <<<< true? 3 set_pc(RVC_RS1 & ~reg_t(1));

What is the correct behavior in this case? • perform jump instruction to PC 0x0 • mark this instruction as illegal.