Exceptions update CSRs while in Debug Mode

Created by: shetalani

RISC-V Specification:

• "When executing code from the optional Program Buffer, the hart stays in Debug Mode and the following apply: Exceptions don't update any registers. That includes cause, epc, tval, dpc, and mstatus. They do end execution of the Program Buffer."

Issue Description:

While in debug mode the instruction ECALL updates some CSRs, while it should not.

Example:

As shown below, the instruction 32'h73 (ecall), decoded at time point t##0 where the current privilege is M and debug_mode is set, updates the MEPC, MCAUSE and MSTATUS registers.

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Product: OneSpin 360 DV-Verify App: RVV Tool's version: 2019.2.2