BUG: ebrk_insn_i set at the same time as illegal_inst_i, should be one hot

Created by: dspg-arch1

this is an actual cause of a unique case violation.

if (instr_i[11:7] == 5'b0) begin // c.ebreak -> ebreak instr_o = {32'h00_10_00_73}; if (instr_i[6:2] != 5'b0) illegal_instr_o = 1'b1;

at the same time an instruction is being decompressed to ebreak and also marked as illegal which cause unique case violation at the next cycle. From our point of view this is a design bug in the riscv_compressed_decoder module which can cause a design instability.

suggested fix:

if (instr_i[11:7] == 5'b0) begin // c.ebreak -> ebreak if (instr_i[6:2] != 5'b0) illegal_instr_o = 1'b1; else instr_o = {32'h00_10_00_73};