Tags

v5.0.0

The major modification in this release is the support of the write-back (WB) policy (in
addition to the write-through (WT) policy). The cache can either implement one of these
policies or both in a per-cacheline basis.

- Added

  - Support of the WB policy.
  - Configuration parameters to choose between WT or WB, or both, at synthesis time.
  - Validation testbench compatible to Verilator.
  - Add a write-policy hint field in the request to select between WT and WB, dinamically.

- Removed

  - WbufSendFeedThrough parameter removed

- Changed

  - Arbitration between cacheable and uncacheable memory requests is done inside the
    HPDcache. The memory interface implements 5 channels, instead of 10.
  - The CMO type is into the operation field of the request (instead of the size field).
  - Select the victim cacheline at cache miss time (before was done on refill time). The
    slot is pre-allocated and written by the miss handler when the refill response arrives.

tag: release version 3.0.0

Added:

- Add support for virtually-indexed addressing

Fixed:

- Fix forwarding logic of uncacheable Icache response in the cva6 cache subsystem.
- Fix wrong mask signal when implementing the MSHR in registers

hpdcache: v2.1.0 release

Added

- Add additional configuration to implement MSHR in registers (when the number
  of entries is low)

Fixed

- Fix cache data SRAM chip-select generation when word width is different than
  64 bits (e.g. 32 bits)

Release version 2.0.0 of the HPDcache

Added

- Add parameters in the HPDcache module to define the types of interfaces to
  the memory
- Add helper verilog header file with macros to ease the type definition of
  interfaces to the memory
- Add new event signals in the HPDCache top module
- Add generic single-port RAM macros with byte-enable signals
- Add parameters in the package to choose between RAM macros implementing
  byte-enable or bitmask for the different RAMs instances
- Add additional assertions to verify parameters
- Add additional configuration signal to inhibit write coalescing in the write
  buffer

Removed

- Remove base_id ports in the HPDCache top module
- Remove nettype (wire,var) in ports as it looks like is badly supported in
  some cases by some simulation tools

Changed

- Split the hpdcache_pkg into: (1) the hpdcache_pkg contains internally defined
  parameters; (2) a new hpdcache_params_pkg that defines user parameters
- New selection policy of ready requests in the replay table. It gives priority
  to requests in the same linked list.
- The write buffer now accepts writes from requesters in a pending slot when it
  is waiting for the internal arbiter to forward the data to the NoC.

Fixed

- Correctly support HPDCACHE_ACCESS_WORDS=1
- Correctly support HPDCACHE_ACCESS_WORDS=HPDCACHE_CL_WORDS
- Fix width of the nlines count register in the HW memory prefetcher.