Writeback to x0

Created by: moimfeld

Hi @Silabs-ArjanB,

In both the "F" and "V" RISC-V standard extensions there exist instructions (e.g. vset{i}vl{i} rd, {...}, csrrw rd, fcsr, rs) that will write back to the general purpose register file only if rd != x0. Is it allowed for a coprocessor to assert writeback in the issue transaction and we in the result transaction even if rd == x0? Or more general, should a core be able to ignore writebacks to x0 (and associated signals) in general?

I know from @michael-platzer that in Vicuna writeback and we are asserted even if rd == x0. The same is true for the floating-point coprocessor I developed a while ago.