Updates to simulation Makefile

Task Outcome

1. Add support for Mentor's Questa SystemVerilog simulator.
2. Add the ability to run individual tests.

Background information

Questa.

At this point there are no rules to support Questa. There are rules for Verilator, Cadence Xcelium (xrun) and Metrics dsim, so it should be straightforward to create new rules for Questa.

Running Individual Tests.

Section 3.2.2 of the Verification Strategy (V0.4) discusses the testbench and testcases in sufficient detail for this task. The Makefile rules and the directory with the testcase assembler code are organized in such a way that the user needs to run all tests in a directory. This is OK for regression, but it is not ideal for development and debug of new tests. Its desirable to be able to specify a single test. This is expected to be a big task as it goes straight to the heart of how testcases and the Makefile are organized.

Location Information

The location of the Makefile in GitHub is https://github.com/openhwgroup/core-v-verif/blob/master/cv32/tests/core/Makefile.

Completion Criteria

1. Questa: when make questa-hello_world (and similar) works the same as make dsim-hello_world (and similar).
2. Ability to specify single test on the command line. E.G make questa TEST=<test_name.S>

Additional context

In the near future, the above Makefile will be replaced by Makefiles in the sim directory: https://github.com/openhwgroup/core-v-verif/tree/master/cv32/sim/core https://github.com/openhwgroup/core-v-verif/tree/master/cv32/sim/uvmt_cv32