Counters test-program fails in the presense of memory stalls

I am not yet certain this sighting is a real issue, but I want to record this information for later analysis.

The counters testcase (cv32/tests/programs/custom/counters) has been passing reliably for a couple of weeks now. The test is now failing intermittently in regression when stalls on the memory interface are enabled.

UVM_INFO @ 1.000 ns : mm_ram.sv(211) reporter [RNDSTALL] INSTR OBI stall enable: 1
UVM_INFO @ 1.000 ns : mm_ram.sv(212) reporter [RNDSTALL] INSTR OBI stall mode:   1
UVM_INFO @ 1.000 ns : mm_ram.sv(213) reporter [RNDSTALL] INSTR OBI stall gnt:    1
UVM_INFO @ 1.000 ns : mm_ram.sv(214) reporter [RNDSTALL] INSTR OBI stall valid:  0
UVM_INFO @ 1.000 ns : mm_ram.sv(215) reporter [RNDSTALL] INSTR OBI stall max:    2
UVM_INFO @ 1.000 ns : mm_ram.sv(216) reporter [RNDSTALL] DATA  OBI stall enable: 1
UVM_INFO @ 1.000 ns : mm_ram.sv(217) reporter [RNDSTALL] DATA  OBI stall mode:   2
UVM_INFO @ 1.000 ns : mm_ram.sv(218) reporter [RNDSTALL] DATA  OBI stall gnt:    0
UVM_INFO @ 1.000 ns : mm_ram.sv(219) reporter [RNDSTALL] DATA  OBI stall valid:  1
UVM_INFO @ 1.000 ns : mm_ram.sv(220) reporter [RNDSTALL] DATA  OBI stall max:    1

The failure signature is:

instret count = 4
pass
Jump register hazards count = 0
fail

Steps to Reproduce

Fails on the head of the master branch of core-v-verif

make test SIMULATOR=dsim TEST=counters DSIM_SEED=982826100

Additional context

This test and seed combination always fails in the same manner with dsim 20200720.11.0 under multiple platforms. It is a given that the same seed will not produce the same results with different simulators.