Compliance test cases have mismatches in signature checks

Created by: Silabs-ArjanB

In core-v-verif (hash 891805fe) the ci_check fails on xrun-illegal and xrun-hello-world. There are also various 'compliance test failures' visible but they do not end up in below summary:

TOOL: xrun(64) 20.06-a001: Exiting on Sep 23, 2020 at 05:26:29 CDT (total: 00:00:08) ../cv32/sim/uvmt_cv32/xrun_results/illegal/xrun-illegal.log: SIMULATION FAILED - ABORTED ../cv32/sim/uvmt_cv32/xrun_results/hello-world/xrun-hello-world.log: SIMULATION FAILED - ABORTED ../cv32/sim/uvmt_cv32/xrun_results/corev_jump_stress_test_1/xrun-corev_jump_stress_test_1.log: SIMULATION PASSED ../cv32/sim/uvmt_cv32/xrun_results/corev_arithmetic_base_test_0/xrun-corev_arithmetic_base_test_0.log: SIMULATION PASSED ../cv32/sim/uvmt_cv32/xrun_results/corev_jump_stress_test_0/xrun-corev_jump_stress_test_0.log: SIMULATION PASSED ../cv32/sim/uvmt_cv32/xrun_results/corev_arithmetic_base_test_1/xrun-corev_arithmetic_base_test_1.log: SIMULATION PASSED ../cv32/sim/uvmt_cv32/xrun_results/corev_rand_instr_test_0/xrun-corev_rand_instr_test_0.log: SIMULATION PASSED ../cv32/sim/uvmt_cv32/xrun_results/riscv_ebreak_test_0/xrun-riscv_ebreak_test_0.log: SIMULATION PASSED ../cv32/sim/uvmt_cv32/xrun_results/csr_instructions/xrun-csr_instructions.log: SIMULATION PASSED ../cv32/sim/uvmt_cv32/xrun_results/corev_rand_instr_test_1/xrun-corev_rand_instr_test_1.log: SIMULATION PASSED ../cv32/sim/uvmt_cv32/xrun_results/riscv_arithmetic_basic_test_0/xrun-riscv_arithmetic_basic_test_0.log: SIMULATION PASSED

CI Check FAILED with unknown failures.