[cv_dv_utils pulse gen] To add pulse generator(new uvm driver) in cv_dv_utils

Created by: khandelwaltanuj

Hello,

A new uvm driver pulse generator is added in the cv_dv_utils.

Here is a little detail. The Pulse Gererator is a SystemVerilog UVM module which is used to configure and generate pulses. Pulse Generator can be configured to generate multiple pulses. A pulse can be a sysncronous pulse with respect to a clock or an asynchronous pulse. Timeunit of pico second is used to genarate an asynchronous pulse.

The new driver has been tested in the TB of HPDCache, where it is used to generator the signal flush. And we would like to commit it to the open source.

Thanks and regards Tanuj Khandelwal