Mention of UVM run_phase in uvm_tests.rst is incorrect

Email from dave.rich@siemens.com:

I was reading the text on this page: https://github.com/openhwgroup/core-v-verif/blob/master/docs/VerifStrat/source/uvm_tests.rst

In the run phase the base test will assert the fetch_en input to the core which signals it to start running. The timing of this is randomized but keep in mind that it will always happen after reset is de-asserted (because resets are done in the reset phase, which always executes before the run phase).

This is not correct. The UVM’s run_phase starts at time 0 in parallel with the reset_phase. You use run_phase with components that do not need to be aware of other phases, or if your sequences are set up to be unaware of phases. (i.e. you would start a reset_sequence in the run_phase, followed by other sequences. Usually monitors are not aware of other phases.

But if you do choose to use the reset_phase, then you would use the main_phase instead of the run_phase.

See https://www.chipverify.com/uvm/uvm-phases

-Dave