ISACOV: Incorrect length for rs1 & rs2 & rd in some compressed instructions

Created by: AyoubJalali

Hello, @silabs-robin I notice in https://github.com/openhwgroup/core-v-verif/blob/master/lib/uvm_agents/uvma_isacov/cov/uvma_isacov_cov_model.sv there is some incorrect coverpoint declaration for some C_TYPE like (CIW, CL, CS, CB), https://github.com/openhwgroup/core-v-verif/blob/05ba4eb0cf6296bf35f487fbe2ab01e532d0fe26/lib/uvm_agents/uvma_isacov/cov/uvma_isacov_cov_model.sv#L1293, so in this example we create a coverpoint for a 5 bits register (32 auto bins), and we know that for CB_TYPE the rs1 is only a 3 bits (8 auto bins), so that affect the real total value of the coverage. So for now a had a simple idea to correct that, instead of create a coverpoint for rs1, we can create it just for 3 bits, rs1[2:0],but i'm not sure if we should take the LSB 3 bits, or MSB, because for rs1'=000 means the register x8, if what i'm saying correct, should be more simple to add a more variable for the C extension, then connect it.