Overview of open issues related to CV32E40X/CV32E40S Imperas ISS

Created by: Silabs-ArjanB

This issue will be used to provide an overview of open issues related to CV32E40X/CV32E40S Imperas ISS. The list will be continuously updated. Issues that exist on both CV32E40X and CV32E40S will not necessarily be mentioned twice.

• CV32E40X

1. Resolved - No schedule supplied for ISS 0.3.0.
2. Resolved - mret in debug mode increments minstret (https://github.com/openhwgroup/cv32e40x/issues/558).
3. Resolved - ISS mismatch if debug entry occurs on first instruction of NMI ISR handler.
4. Resolved - (0.2.0) Default ecode_mask=255 incorrect (should be 2047)
5. Resolved - (0.2.0) Default mtvec_mask=0xffff_ff01 incorrect (should be 0xffff_ff81)
6. Resolved - (0.2.0) Default tcontrol_undefined incorrect (Default NUM_TRIGGERS parameter = 1, tcontrol should be present by default, and should be conditionally enabled/disabled based on number of triggers implemented)
7. Resolved - (0.2.0) misa.B sometimes set, 'add_Extensions' issue (see text below in this issue)
8. Resolved - (0.2.0) Debug cause dcsr[8:6] mismatch when external debug is taken over single step (see text below in this issue)
9. Resolved - (0.2.0) https://github.com/openhwgroup/core-v-verif/issues/1327

• CV32E40S

1. Resolved - No schedule supplied for ISS 0.3.0.
2. Open - (0.2.0) Default value instret_undefined=T removes minstret (which should be present). Too strict coupling between instret and minstret.
3. Open - (0.2.0) New model Documentation lacks provisions for bitmanip-extensions
4. Awaiting merge - (0.2.0) Bitmanip enable-overrides appears to not function correctly (e.g. ctz triggers illegal instruction when enabled)
5. Awaiting merge - (0.2.0) Default ecode_mask=255 incorrect (should be 2047)
6. Awaiting merge - (0.2.0) Default mtvec_mask=0xffff_ff01 incorrect (should be 0xffff_ff81)
7. Open - (0.2.0) Default tcontrol_undefined incorrect (Default NUM_TRIGGERS parameter = 1, tcontrol should be present by default, and should be conditionally enabled/disabled based on number of triggers implemented)
8. Resolved - (0.2.0) misa.X should be 1
9. Resolved - (0.2.0) cycle_undefined=T removes mcycle csr (https://github.com/openhwgroup/core-v-verif/issues/1326)
10. Open - dcsr.prv seems not implemented - https://github.com/openhwgroup/core-v-verif/issues/1366