Unexpected DSIM error: "No clocking event is specified or can be inferred"

A recent update to uvmt_cv32e40x_interrupt_assert.sv, see line 205 and line 432, causes compile errors under dsim:

=E:[MissingClockingEvent]:
    No clocking event is specified or can be inferred    

    /home/mike/GitHubRepos/strichmo/core-v-verif/cv32e40x/merge_dev_to_rel_57/cv32e40x/tb/uvmt/uvmt_cv32e40x_interrupt_assert.sv:207:21

[snip]

The code in question compiles and simulates under Xcelium. I do not see a reason for this error, so a hot-fix will be applied to exclude these code segments from dsim compilation. As these are coverage properties, the fidelity of the testing will not be affected (but coverage will). An issue will be raised with Metrics as well.