Create documentation for CV32E40P corev-dv extensions

At the time of this writting, all cores supported by core-v-verif use the Google riscv-dv instruction stream generator and the E40 cores extend riscv-dv to implement corev-dv, a core-specific ISG. The extensions are maintained in core-v-verif/<core>/env/corev-dv. When we first started using riscv-dv the number of corev-dv extensions was small and the relative complexity of each extension was simple. Since then, our use of riscv-dv has grown in sophistication and the number and complexity of corev-dv extensions has grown significantly. A good example of this can be seen in pull-request #1067.

The purpose of this task is to launch a series of tasks to document the implementation and usage of corev-dv for CV32E40P, E40X and E40S. This specific task will focus on the E40P.

Task Outcome

As we have not yet done this type of documentation it is not completely clear what "done" looks like for this task. The following is suggested. For each class extension add a section in the README that:

• names the extension.
• provides a rationale for the creation of the extension (extra points if the rationale is tied to specific functional coverage goals).
• includes human readable description of what the extension does and whether it has dependencies on the external environment such as a test-program or the BSP.
• provides a special compile/run-time usgage instructions.

Completion Criteria

A completed pull-request to update the README for the CV32E40P's corev-dv extensions.