Re-think FPGA specific modules

Created by: zarubaf

Currently the FPGA and ASIC specific modules are ifdefed and scattered throughout the code. I would propose two fixes to that:

• SRAMs are wrapped in technology unspecific ways. During implementation, they can be substituted with the tech specific versions. Similar to other tech specific components (see tech_cells_generic).
• For the clock generator I would propose we pull out the clock into the top-level. For the FPGA we can instantiate the clock generator in xilinx_core_v_mcu.v (or use the block generator). For the ASIC I would suggest we keep core_v_mcu_chip.sv where we instantiate the FLL. That would also allow us to remove the VHDL stub of FLL which is a. annoying with Verilator and b. contains too much information for RTL sim IMHO.