drivers/clk · v4.14.215 · Eclipse Projects / Oniro Core / linux

clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9

Terry Zhou authored 4 years ago

commit 6f37689c upstream.

There is an error in the current code that the XTAL MODE
pin was set to NB MPP1_31 which should be NB MPP1_9.
The latch register of NB MPP1_9 has different offset of 0x8.

Signed-off-by: Terry Zhou <bjzhou@marvell.com>
[pali: Fix pin name in commit message]
Signed-off-by: Pali Rohár <pali@kernel.org>
Fixes: 7ea82504 ("clk: mvebu: Add the xtal clock for Armada 3700 SoC")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20201106100039.11385-1-pali@kernel.org


Reviewed-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

201ec6f9

History

201ec6f9 4 years ago

History

Name	Last commit	Last update
..
at91
axis
axs10x
bcm
berlin
h8300
hisilicon
imgtec
imx
ingenic
keystone
loongson1
mediatek
meson
microchip
mmp
mvebu
mxs
nxp
pistachio
pxa
qcom
renesas
rockchip
samsung
sirf
socfpga
spear
st
sunxi-ng
sunxi
tegra
ti
uniphier
ux500
versatile
x86
zte
zynq
Kconfig
Makefile
clk-asm9260.c
clk-axi-clkgen.c
clk-axm5516.c
clk-bulk.c
clk-cdce706.c
clk-cdce925.c
clk-clps711x.c
clk-composite.c
clk-conf.c
clk-cs2000-cp.c
clk-devres.c
clk-divider.c
clk-efm32gg.c
clk-fixed-factor.c
clk-fixed-rate.c
clk-fractional-divider.c
clk-gate.c
clk-gemini.c
clk-gpio.c
clk-hi655x.c
clk-highbank.c
clk-hsdk-pll.c
clk-max77686.c
clk-moxart.c
clk-multiplier.c
clk-mux.c
clk-nomadik.c
clk-nspire.c
clk-oxnas.c
clk-palmas.c
clk-pwm.c
clk-qoriq.c
clk-rk808.c
clk-s2mps11.c
clk-scpi.c
clk-si514.c
clk-si5351.c
clk-si5351.h
clk-si570.c
clk-stm32f4.c
clk-stm32h7.c
clk-tango4.c
clk-twl6040.c
clk-u300.c
clk-versaclock5.c
clk-vt8500.c
clk-wm831x.c
clk-xgene.c
clk.c
clk.h
clkdev.c