Overview: Implement plcgen2 in ESCET.
Original description
plcgen2 is another PLC code generator, built as a successor to the successor of cif2plc.
The reason for building another version is that while cif2plc is working, it linearizes the CIF model to a single state model with edges for each event, typically with very long and complicated guards.
While this is fine from a computing point of view, it is less than useful in practice where technicians performing maintenance and repairs on the physical systems must understand the code on-site.
At the time, Ferdie looked at the problems around using a CIF model as a controller, addressed the fundamental issues such as confluence and finite response, as well as how to improve on the readability of the generated code. For details, see [1], in particular Chapter 4.
Most of the ideas were implemented in plcgen as well as other improvements like generating IO code with hardware addresses. That generator was successfully used in the project. At the very end though, one of the conclusions was that the generated code was 'stupid'. Weird long names were introduced, silly statement sequences were generated. The underlying reason for this was that the text-based cif2plc backend-storage was still used for storing generated PLC code, the generator decided on one of a few fixed templates for each event based on analysis of the input. To improve you would need to look at and tweak the result after generating the code, but in plcgen that means analysing and tweaking the generated text which is not doable in a reliable way.
A next-gen PLC code generator was thus considered useful, dubbed plcgen2, that has a PLC language meta-model as back-end storage, and a pretty-printer to convert to text. It also addresses some other points in plcgen as usual.
Like plcgen, plcgen2 was also successfully used in the project although it's less finished. It only supports Siemens-S7 and ABB PLCs, and has only made limited use of having a PLC model.
Examples of the latter are resolving old to new state with a single set of state variables by analysis of the read/write patterns of variables, and inlining POU-calls.
As plcgen2 will play an important role in the project(s) in the future, it was considered useful to port that program into ESCET. In addition, from an ESCET point of view, getting more readable output and a more flexible back-end for generating PLC code looks like a good step.
Proof of concept
A proof of concept version of the new PLC code generator was made available via this issue and merge request !357 (closed). It has a sticky build on Jenkins. It has since been re-implemented from scratch and improved upon. A first release is part of %v2.0, see #676 (closed). After the %v2.0 release, we should:
- Close the merge request.
- Remove the branch.
- Remove the sticky build.