Possible spi_fifo.sv bug

Placeholder Rose Thompson
2026-01-29T14:47:54Z

I believe there is a bug in the fifo by code inspection and FPGA debugging. It appears possible to stall a load of the RXDATA register and potentially read out the head of the fifo and then immediately read out the next value. The fifo works by combinationally reading out the head and sampling this data on the cycle before PSEL and PENABLE are high. However if the the load is stalled the head pointer is still incremented so the fifo changes the output data while the instruction is stalled. Several times while debugging the FPGA zsbl I found what appeared to be reading the wrong value from the FIFO, but after fixing the zsbl issues I haven't been able to reproduce this error.