[BUG] Confusing overriding of config in FPGA toplevel

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2026-03-18T14:45:10Z

The FPGA toplevel (`ariane_xilinx.sv`) overrides a few of the core configs, without a clear justification for which ones are being overruled. This led to some surprise and a (longer than I'd care to admit) debugging headache.

In particular, is there a reason why ZiCond in particular needs to be disabled for FPGA?
https://github.com/openhwgroup/cva6/blob/0e04a86b1316dfcd59b5f17298260cc5ea10af3e/corev_apu/fpga/src/ariane_xilinx.sv#L204

It seems like having a separate config would be preferred to overrulling the parameter specifically for FPGA builds. Currently, there's a divergence between the config that will be tested in CI and the one that will get built for FPGA, even if they use the same `core/include` config.

Similarly, the non-idempotent regions are configured in `ariane_xilinx.sv`, but the cacheable regions need to be configured in the `core/include` core config: I see no reason to handle these in two separate places, when they really need to be consistent for things to work:

https://github.com/openhwgroup/cva6/blob/0e04a86b1316dfcd59b5f17298260cc5ea10af3e/corev_apu/fpga/src/ariane_xilinx.sv#L205-L207
https://github.com/openhwgroup/cva6/blob/0e04a86b1316dfcd59b5f17298260cc5ea10af3e/core/include/cv64a6_imafdch_sv39_config_pkg.sv#L136-L144

Converesely, one feature that might actually benefit from being overridden in the FPGA toplevel is RVFI: we've disabled it in our fork for FPGA builds as we see it showing up in timing paths, but it seems the simulators rely on it in some cases, e.g. to exit the simulator when a test finishes.