[BUG] Incorrect `fflags.NV` set by fleq.s/d with Finite Operands

Placeholder Sherlock
2025-12-31T06:06:07Z

The CVA6 processor incorrectly updates the `fflags CSR` when executing the `fleq.s` and `fleq.d` instructions (Zfa extension). Specifically, it sets the Invalid Operation (NV) flag even when both operands are normal finite numbers.
> According to the RISC-V Zfa specification and IEEE 754-2019, quiet comparison instructions should only signal NV if at least one operand is a Signaling NaN (SNaN). Comparing finite numbers must never set the NV flag.

### Environment
- Processor: RV64, FLEN=64, scalar FP present (F/D/Zfh enabled so S/H/D compares decode)
- Reference Model: Spike (ISA Simulator)

### Instruction & Operand Details

The discrepancy was observed in the following instruction sequence:
- Instruction: `fleq.s x15, f18, f19`
- Machine Code: 0xa13947d3
- Operands:
- `f18` = `0x7db30525bc6b6a36` (Low 32-bit: 0xbc6b6a36)
- `f19` = `0x39d16358ac501c87` (Low 32-bit: 0xac501c87)

**Operand Analysis (Single Precision)**
Value | Hex (32-bit) | Type | Exponent (Biased)
-- | -- | -- | --
rs1 (f18) | 0xbc6b6a36 | Finite (Negative) | 0x78 (120)
rs2 (f19) | 0xac501c87 | Finite (Negative) | 0x58 (88)

**Observed vs. Expected Behavior**

Feature | CVA6 (DUT) | Spike (Reference) | Result
-- | -- | -- | --
x15 (Result) | 0x0 | 0x0 | Pass
fflags (NV bit) | 0x10 (Set) | 0x00 (Not set) | FAIL

Nothe that: fleq.d also set the incorrect NV flag.

**Minimal Assembly Code for Reproduing**
```assembly
li x8, 0x7db30525bc6b6a36
fmv.d.x f18, x8
li x8, 0x39d16358ac501c87
fmv.d.x f19, x8
fleq.s x15, f18, f19
csrrs x20, fflags, x0
csrw fcsr, x0
fleq.s x15, f18, f19
csrrs x20, fflags, x0
```