[BUG] Interrupts wrongly masked by fetch side exceptions

Placeholder Sven Beyer
2026-02-05T16:11:47Z

With Questa Processor, we found a scenario where CVA6 raises a fetch side exception (concretely fetch access fault). However, an interrupt is expected. This seems due to the code structure
`if (~ex_i.valid) begin`
` // synch exceptions relying in fetched instruction word, so must not evaluate since fetch side exception means no instruction word to decode`
` // interrupts should be evaluated regardless of fetch side exception`
`end`
`// debug request`
So debug requests indeed always take priority, but regular interrupts only take priority over exceptions from decode like illegal instruction or environment call, but a fetch side exception like a fetch access fault simply blocks evaluation of all interrupt conditions.