[BUG] Supervisor timer interrupt unexpectedly masked

Placeholder Sven Beyer
2026-02-04T12:46:20Z

We have investigated a 64-bit cva6 configuration with Supervisor mode with Questa Processor and found a mismatch regarding Supervisor interrupts.
The situation:
We are executing in M mode, mideleg.SEI is set and irq_i[1] is active. So there is a Supervisor External Interrupt, but due to the delegation, it is correctly not taken since it is masked in M mode. However, there is an additional mip.STI active, so there is a pending Supervisor Timer Interrupt as well and that one is not delegated to S mode. With the current interrupt logic in CVA6, this gets masked since SEI is computed as "winner" over STI and then not taken due to its delegation. Instead, SEI should just be masked for M mode prioritization, allowing to simply take the STI to M mode.
Also consider the Sail model as reference - function getPendingSet separately considers
let pending_m = mip.bits & mie.bits & ~(mideleg.bits);
let pending_s = mip.bits & mie.bits & mideleg.bits;
for prioritization, so the delegated SEI is masked, leaving the STI to be taken in M mode.