[XIF] Interrupts cleared too late

Placeholder Arjan Bink
2022-08-29T13:00:31Z

If an interrupt is cleared via a (non-bufferable) store, then the interrupt on irq_i will go low in the cycle after the store instruction left the WB stage. As the irq_i lines are registered inside the core, a following instruction can still get to see the interrupt that was supposed to be cleared.