Builtin optimisation enhancement

Placeholder MaryBennett
2024-08-16T08:58:33Z

The CORE-V builtins can be enhanced by expanding the rtl for each instruction. This would allow gcc to pattern match to these builtins.
More testing with a simulator would be required.

Added, untested with simulator:

- [x] XCVmac
- [x] XCValu
- [x] XCVelw
- [x] XCVbi
- [x] XCVmem
- [x] XCVbitmanip
- [ ] XCVsimd
- [x] XCVhwlp