Polara ASIC Chip Bring Up Merge

Placeholder Raphael Rowley
2026-03-29T08:32:03Z

This pull request includes the work done from May-December 2024 which focused on implementing a chipset on the Genesys 2 FPGA board to test the Polara ASIC. More information is included in the attached pdf.
[2024_12_18_pull_request.pdf](https://github.com/user-attachments/files/18223110/2024_12_18_pull_request.pdf)