Default clock selected is h_clk for counter of APB Timer IP

Placeholder Syed Rameez
2026-02-12T15:40:55Z

APB_TIMER uses the default clock as h_clk for the counter operations. That is the counter is incremented for each positive edge of the h_clk clock.

For each APB write and read to the registers, the APB bus consumes 2 or 3 h_clk clock cycles.

Let us consider the example of FW reading the register TIMER_VAL_LO register :
1. The APB_TIMER counter is configured in such a way that REF_CLK_EN bit of CFG_REG_LO is '0'. (Default value) Where the clock period h_clk is 2.5 ns.
2. FW issues a read command which consumes 3 clock cycles. (synchronization with h_clk, setup and access time delays)
3. When the FW initiates the request for register read at 10 ns.
4. APB BUS consumes 7.5 ns of time and It will get the TIMER_VAL_LO at 17.5 ns.
5. Here, the FW compares the expected TIMER_VAL_LO at 10 ns with the of TIMER_VAL_LO preovided by RTL at 17.5 ns.
Summary: We wanted to understand how the APB TIMER RTL and FW synchronization happen when the APB_TIMER is configured to count for each positive edge of the h_clk clock.

Clock period calculations are taken from the below TB and test:

ref_clk_i is driven to (10 MHz or 100ns) by the Perceptia PLL pd_gf22_PLL02_model.v
for REF_CLK_PERIOD in the file https://github.com/openhwgroup/core-v-mcu/blob/767916ceb2f08cbee0510accf794660d2f9d94f9/tb/core_v_mcu_tb.sv#L18

FW configurations done to get the h_clk driven to (400 Mhz - or 2.5 ns ) for the case Perceptia https://github.com/openhwgroup/core-v-mcu-cli-test/blob/main/cli_test/target/core-v-mcu/core-v-mcu.c