RTL code non compliant with verilator

Placeholder Syed Rameez
2026-02-11T18:54:42Z

We have tried to convert the system verilog to C++ code using the verilator. we have faced a couple of errors and we had to change the system verilog RTL code to fix these errors.

The following were the below two changes:

1. Adding default statement to a case in the APB read logic.
```
default:
PRDATA = 32'b0;
```

2. Removing the combinational logic for resets and adding it to the sequential logic.
```

// RESET LO
// if (s_reset_count_lo == 1'b1)
// s_cfg_lo[`RESET_BIT] = 1'b0;

// RESET HI
// if (s_reset_count_hi == 1'b1)
// s_cfg_hi[`RESET_BIT] = 1'b0;

end

// sequential part
always_ff @(posedge HCLK, negedge HRESETn)
begin
if(~HRESETn)
begin
s_cfg_lo_reg <= 32'b0;
s_cfg_hi_reg <= 32'b0;
s_timer_cmp_lo_reg <= 32'b0;
s_timer_cmp_hi_reg <= 32'b0;
end
else
begin
// Default: Update registers with values calculated in always_comb
s_cfg_lo_reg <= s_cfg_lo;
s_cfg_hi_reg <= s_cfg_hi;
s_timer_cmp_lo_reg <= s_timer_cmp_lo;
s_timer_cmp_hi_reg <= s_timer_cmp_hi;

// --- FIX FOR UNOPTFLAT: Sequential Clear ---
// If the reset signal was active in this cycle,
// ensure the bit is cleared in the register for the NEXT cycle.
if (s_reset_count_lo) begin
s_cfg_lo_reg[`RESET_BIT] <= 1'b0;
end

if (s_reset_count_hi) begin
s_cfg_hi_reg[`RESET_BIT] <= 1'b0;
end
end
end
```