Clarification of memories accessed by uDMA core

As per the details mentioned at https://docs.openhwgroup.org/projects/core-v-mcu/doc-src/high_level_architecture.html#micro-dma-subsystem , uDMA cannot access the non-interleaved memories . However, the RTL implementation at **** does not impose such a restriction.

s_l2_dest mentioned in the above snippet is hardocded to 0, which means l2_addr_o[31:24] is always set to 0x1C. Now, if we look at below table in https://docs.openhwgroup.org/projects/core-v-mcu/doc-src/mmap.html it says both interleaved and non-interleaved memory starts at 0x1c.

Please help to resolve this ambiguity.