Futurewei 20210308

Created by: noahsherrill

Summary of changes:

• Added support for RV32G
• Added support for multiprocessing instruction generation
• Fixed the following issues:
  • Exception handlers were sometimes generated in the boot region or overlapping the initial PC
  • Memory was not initialized for one of the target address ranges in a vector strided instruction with a negative stride value
  • Page faults were being unintentionally triggered for load and store instructions targeting a previously used page
  • Leaf megapage descriptors were sometimes encoded as non-leaf descriptors
  • A few CSRs did not have boot instructions generated for them
  • A few vector CSRs were not properly initialized
  • PC value was not always updated correctly after executing an xRET instruction
  • An exception in the end of test sequence caused a failure to detect the end of the test
  • There was insufficient instruction space allocated for some particularly long boot sequences
  • Re-execution detection failed to detect compressed instructions
  • Sequence.getPageInfo() was failing when invoked in a test template
  • Handcar was releasing memory regions reserved by LR instructions after each instruction step
  • Miscellaneous other minor issues
• Made Handcar build script a little easier to use
• Improved generation speed of some vector load and store instructions
• Created clearer directory structure for architecture data files