Fix incorrect debug_cause priority against riscv-debug 1.0.0-STABLE

Created by: davideschiavone

The relevant page [Debug Spec v1.0.0-STABLE, p.53] gives the following priorities for resolving multiple concurrent reasons for entering debug mode....

DCSR.cause : Explains why Debug Mode was entered.

When there are multiple reasons to enter Debug Mode in a single cycle, hardware should set cause to the cause with the highest priority. 1: An ebreak instruction was executed. (priority 3) 2: A Trigger Module trigger fired with action=1. (priority 4) 3: The debugger requested entry to Debug Mode using haltreq. (priority 1) 4: The hart single stepped because step was set. (priority 0, lowest) 5: The hart halted directly out of reset due to resethaltreq. (priority 2) It is also acceptable to report 3 when this happens. 6: The hart halted because it’s part of a halt group. (priority 5, highest) Harts may report 3 for this cause instead.

Other values are reserved for future use.