hpdcache: TB changes aligned to new RTL with write through implementation

Created by: khandelwaltanuj

Hello,

This bench is a ongoing work. After a lot of changes in RTL in last few weeks, it remains relatively unstanble. In its current state, all error responses from memory respose model are disabled. The clock exact sv based PLRU is commented. And the directed PLRU test are only working in the case of write through write policy.

Thanks and Regards Tanuj Khandewel