CORE-V: Auto-generation for Post-Increment Load & Store Instructions and Register-Register Load & Store Instructions

Created by: NandniJamnadas

Post-Increment load and store instructions perform a load, or a store, respectively, while at the same time incrementing the address that was used for the memory access. Since it is a post-incrementing scheme, the base address is used for the access and the modified address is written back to the register-file.

There are versions of those instructions that use immediate and those that use registers as offsets. The base address always comes from a register.

• gcc/common/config/riscv/riscv-common.cc: Defined xcvmem extension.

• gcc/config/riscv/corev.md: Implemented RTL pattern for CORE-V post-inc load/store and reg-reg load/store:

  • cv_load<mode>_postinc,
  • cv_load_<optab><SHORT:mode>_postinc,
  • cv_store<mode>_postinc,
  • cv_load<mode>,
  • cv_load<mode>,
  • cv_load_<optab><SHORT:mode>,
  • cv_store<mode>.

• gcc/config/riscv/predicates.md: Implemented mem_post_inc and mem_plus_reg predicate and modified move_operand.

• gcc/config/riscv/riscv-opts.h: Created Mask and Target macros for CORE-V post-inc load/store.

• gcc/config/riscv/riscv-protos.h: Defined riscv_legitimate_post_inc_p to verify if post inc instructions are valid.

• gcc/config/riscv/riscv.cc:

  • Defined and implemented a new RISC-V address type: ADDRESS_REG_INC.
  • Implemented a POST_MODIFY case in riscv_classify_address.
  • Modified the PLUS case for reg-reg load/store under XCVMEM target.
  • Implemented riscv_legitimate_post_inc_p.
  • Modified riscv_output_move to include ADDRESS_REG_INC

• gcc/config/riscv/riscv.h: Defined CORE-V Macros for post-inc:

  • HAVE_POST_MODIFY_DISP
  • HAVE_POST_MODIFY_REG
  • Modified INDEX_REG_CLASS to accept GR_REGS under XCVMEM target.

GCC Compilation Tests for

• Post Increment Register-Immediate Load/Store
• Post Increment Register-Register Load/Store
• Regiser-Register Load/Store

All post-increment tests do not support optimisation levels -O0, -Os, -Og, -Oz.

• gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-1.c: Created.
• gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-2.c: Likewise.
• gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-3.c: Likewise.
• gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-1.c: Likewise.
• gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-2.c: Likewise.
• gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-3.c: Likewise.
• gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-1.c: Likewise.
• gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-2.c: Likewise.
• gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-3.c: Likewise.
• gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-1.c: Likewise.
• gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-2.c: Likewise.
• gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-3.c: Likewise.
• gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-1.c: Likewise.
• gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-2.c: Likewise.
• gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-3.c: Likewise.
• gcc/testsuite/gcc.target/riscv/cv-mem-sb-compile-1.c: Likewise.
• gcc/testsuite/gcc.target/riscv/cv-mem-sb-compile-2.c: Likewise.
• gcc/testsuite/gcc.target/riscv/cv-mem-sb-compile-3.c: Likewise.
• gcc/testsuite/gcc.target/riscv/cv-mem-sh-compile-1.c: Likewise.
• gcc/testsuite/gcc.target/riscv/cv-mem-sh-compile-2.c: Likewise.
• gcc/testsuite/gcc.target/riscv/cv-mem-sh-compile-3.c: Likewise.
• gcc/testsuite/gcc.target/riscv/cv-mem-sw-compile-1.c: Likewise.
• gcc/testsuite/gcc.target/riscv/cv-mem-sw-compile-2.c: Likewise.
• gcc/testsuite/gcc.target/riscv/cv-mem-sw-compile-3.c: Likewise.