CORE-V: Bit Manipulation bitrev builtin update

Created by: NandniJamnadas

Changed operand order from rd,rs1,Is3,Is2 to
rd,rs1,Is2,Is3 for cv.bitrev to match the CORE-V
Builtin Specifcation.

* gcc/config/riscv/corev.md: Changed operand order for bitrev.
* gcc/testsuite/gcc.target/riscv/
  cv-march-xcvbitmanip-compile-bitrev.c: Updated dg-final directives
  to match output.