Update operand order to match spec for bit manip instructions
Created by: MaryBennett
Fix to issue #32 (closed).
gcc/config/riscv:
- corev.md: Changed operand order from rd,rs1,Is3,Is2 to rd,rs1,Is2,Is3 for cv.bset, cv.bclr, cv.insert, cv.extractu, and cv.extract. This now matches the specification.
gcc/testsuite/gcc.target/riscv:
- cv-march-xcvbitmanip-compile-bclr.c: Updated test to match spec.
- cv-march-xcvbitmanip-compile-bset.c: Likewise.
- cv-march-xcvbitmanip-compile-extract.c: Likewise.
- cv-march-xcvbitmanip-compile-extractu.c: Likewise.
- cv-march-xcvbitmanip-compile-insert.c: Likewise.
==Results==
| Category | Previous | With commit | Delta |
|---|---|---|---|
| Expected passes | 10725 | 10725 | - |
| Unexpected failures | 53 | 53 | - |
| Unexpected successes | - | - | - |
| Expected failures | 6 | 6 | - |
| Unresolved testcases | 6 | 6 | - |
| Unsupported tests | 245 | 245 | - |