CV32E40Pv2 Event Load Update

Created by: NandniJamnadas

Updated Event Load to the builtin specification and documentation: https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md#listing-of-event-load-word-builtins-xcvelw

• gcc/config/riscv/corev.def: Updated builtin cv_elw to cv_elw_elw and updated argument from void_ptr to int_ptr.
• gcc/config/riscv/corev.md: Moved UNSPEC_CV_ELW and event load machine pattern from riscv.md to core.md.
• gcc/config/riscv/riscv-builtins.cc: Added RISCV_ATYPE_INT_PTR argument for integer pointer.
• gcc/config/riscv/riscv-ftypes.def: Added macro with return type unsigned integer and argument type integer pointer.
• gcc/config/riscv/riscv.md: Moved UNSPEC_CV_ELW and event load machine pattern from riscv.md to core.md.
• gcc/doc/extend.texi: Added CORE-V Event Load documentation.
• gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c: Updated test to corresponding argument type.