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Functional verification project for the CORE-V family of RISC-V cores.

Instructions to import Ubuntu guest Virtual Machine for RISC-V development for the VEGA board

The Open Source Developer Forum is a workshop that brings open source software and hardware (chips, boards and systems) developers together to collaborate and learn.

OpenHW Group is a global, not-for-profit organization where hardware and software designers collaborate on open-source cores, IP, tools, and software. It provides infrastructure to host high-quality open-source hardware projects aligned with industry best practices.

CVA6 SDK containing RISC-V tools and Buildroot

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

The rise of advanced driver assistance systems and partially automated driving functions leads to the need of virtual simulation to assess these systems and their effects.

Library for loading and providing data from an OpenDRIVE map

A dual-core lockstep (DCLS) subsystem for the CVA6. Also supports dual-core asymmetric multi-processing (AMP) when lockstep in not needed.

UVM Verification Environment for the CVFPU

The purpose of the repo is to support CORE-V Wally architectural verification

Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.