Explore projects

Repository that maintain the OpenBus Interface spec

This is the CORE-V MCU DevKit project, hosting the open-source artifacts for the CORE-V MCU Development Kit.

Yocto layer for CVA6

4 stage, in-order, compute RISC-V core based on the CV32E40P

RTL code for implementation of dual-core trusted MCU

Issues related to the OpenHW Group infra (GtHub, Mattermost, ...)

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

CORE-V Family of RISC-V Cores

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

Instructions to import Ubuntu guest Virtual Machine for RISC-V development for the VEGA board

OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices.

Instruction Set Generator initially contributed by Futurewei

Functional verification project for the CORE-V family of RISC-V cores.