Explore projects

Yocto layer for CVA6

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

Small and simple APB interrupt controller

CVA6 SDK containing RISC-V tools and Buildroot

Linux kernel source tree

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

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4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

Repository that maintain the OpenBus Interface spec

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

CV32E40X Design-Verification environment

Eclipse/FreeRTOS/core-v-mcu example program

CORE-V MCU UVM Environment and Test Bench

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Unofficial development fork of U-Boot

This is the CORE-V MCU DevKit project, hosting the open-source artifacts for the CORE-V MCU Development Kit.